The asynchronous transfer mode (ATM) protocol architecture is designed to support the transfer of data with a range of guarantees for quality of service. The user data is divided into small, fixed-length packets, called cells, and transported over virtual connections. ATM operates over high data rate physical circuits, and the simple structure of ATM cells allows switching to be performed in hardware, which improves the speed and efficiency of ATM switches.
Figure 23 shows the reference model for ATM. The first thing to notice is that, as well as layers, the model has planes. The functions for transferring user data are located in the user plane; the functions associated with the control of connections are located in the control plane; and the co-ordination functions associated with the layers and planes are located in the management planes.
Figure 23: ATM reference model
The three-dimensional representation of the ATM protocol architecture is intended to portray the relationship between the different types of protocol. The horizontal layers indicate the encapsulation of protocols through levels of abstraction as one layer is built on top of another, whereas the vertical planes indicate the functions that require co-ordination of the actions taken by different layers. An advantage of dividing the functions into control and user planes is that it introduces a degree of independence in the definition of the functions: the protocols for transferring user data (user plane) are separated from the protocols for controlling connections (control plane).
The protocols in the ATM layer provide communication between ATM switches while the protocols in the ATM adaptation layer (AAL) operate end-to-end between users. This is illustrated in the example ATM network in Figure 24.
Two types of interface are identified in Figure 24: one between the users and the network (user-network interface), and the other between the nodes (switches) within the network (network-node interface).
Figure 24: ATM network
Before describing the functions of the three layers in the ATM reference model, I shall briefly describe the format of ATM cells. Figure 25 shows the two basic types of cell.
Figure 25: (a) ATM cells at the user-network interface; (b) ATM cells at the network-node interface
Each ATM cell consists of 53 bytes: the header is five bytes long and the remaining 48 bytes (the cell payload) carry information from higher layers. The only difference between the two types of ATM cell is that the cells at the user-network interface carry a data field for the flow control of data from users. This means that only eight bits are available for virtual path identifiers, rather than 12 bits at the network-node interface.
The virtual connections set up in ATM networks are identified by the combination of the virtual path identifier and virtual channel identifier fields shown in Figure 25. These two fields provide a hierarchy in the numbering of virtual connections, whereby a virtual path contains a number of virtual channels as is illustrated in Figure 26. An advantage of this hierarchy is that in some cases the switching of ATM cells may be based on the virtual path identifier alone.
Figure 26: Virtual path and virtual channel relationship (Source: adapted from ITU-T 1–150, 1999, Figure 1)
how many different virtual connections can exist between a user and an ATM network, and between a node and an ATM network?
Now read the answer
Answer
between a user and an ATM network a total of 24 bits are available for identifying virtual connections; therefore there can be 224 = 16777216 connections. At the network-node interface a total of 28 bits are available, so the number of connections possible is 228 = 268435456.
The payload type field (see Figure 25) identifies the type of cell. I do not intend to describe the specific types of ATM cell, but there are types for carrying user information, signalling information for controlling virtual connections, and management information. There are two basic types of user information cell: one in which congestion has been identified and one in which it has not.
The cell loss priority (CLP) field is a single bit; if the bit is 0 that cell has a high priority, and if the bit is 1 the cell has a low priority. This information may influence the decision whether to discard cells if a network becomes congested.
The header error control field contains a cyclic redundancy check on the other bytes in the header.
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